Test Engineer

Job Description

Queensway, Singapore | Posted on 09/14/2023

Responsible for scan insertion, boundary scan, MBIST, ATPG forultra-low power SoC based on subthreshold operation using standard EDAtools.

Develop and implement low-power DFT architecture and infrastructure.

Generate structural test vectors, analyze and improve coverage, testtime and test cost.

Perform pre/post-layout scan and MBIST simulations.

Work with designers on STA, physical, power and logical issuesrelated to DFT.

Work with test engineers to bring up test vectors on silicon.

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