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UTAC

Ang Mo Kio / Global

Corporate R&D Process Development Engineer (Underfill)

Job Description

Position Summary The Underfill Process Development Engineer is responsible for developing, optimizing, qualifying, and sustaining underfill processes for advanced semiconductor packaging technologies. This role focuses on process characterization, material evaluation, reliability improvement, yield enhancement, and equipment optimization for flip chip, SiP and advanced package assemblies.

The engineer will work closely with customers, material suppliers, equipment vendors, manufacturing teams, and reliability engineers to develop robust and cost-effective underfill solutions that meet quality, reliability, and productivity requirements.

Key Responsibilities

Develop and optimize capillary underfill and advanced dispensing processes for semiconductor packages.

Establish process windows for underfill dispense, flow, cure, and post-cure operations.

Evaluate new underfill materials and dispensing technologies.

Define and execute Design of Experiments (DOE) to improve process capability and performance.

Develop processes for advanced packaging applications including Flip Chip, 2.5D, and SiP technologies.

Requirements

Education

Bachelor's Degree in:

Chemical Engineering

Materials Science Engineering

Mechanical Engineering

Electronics Engineering

Semiconductor Engineering

Master's Degree preferred.

Experience

3–10 years of semiconductor packaging process development experience.

Experience in underfill process development preferred.

Experience in advanced packaging technologies is highly desirable.

Technical Skills

Required

Underfill dispensing and curing processes (Hands on experience with Asymtek, NSW and leading dispensers)

DOE and statistical analysis

Process characterization and optimization

Root cause analysis methodologies

Yield improvement techniques

Semiconductor packaging fundamentals

SPC, FMEA, Control Plans

Failure analysis methodologies

Preferred

Flip Chip Packaging

System-in-Package (SiP)

2.5D/3D Packaging

Warpage characterization

Material characterization techniques

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