Lead Integration Yield Defect Engineer

Job Description

Vanguard International Semiconductor Corporation (VIS) in Singapore seeks a supervisor for YDD Associate Engineers and wafer tech operators to ensure continuous 24/7 inline operations. You will train engineers on recipes and defect sources, and maintain SOPs while supporting internal and external audits.

You will operate FIB/SEM/EDX for inline failure analysis, create recipes in YDD tools, manage defect data, and drive continuous yield improvements with cross-functional teams.

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Vanguard International Semiconductor Corporation (VIS)

Lead Integration Yield Defect Engineer

Job Description

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