Start Your Search Here

Job Search

UST

Singapore / Global

Senior Design Verification Engineer

Job Description

Apply UVM (Universal Verification Methodology), SystemVerilog, Verilog, and SVA (SystemVerilog Assertions) languages in verification tasks

Develop and implement state-of-the-art verification methodologies, including UVM, C/C++, co-simulation, system emulation, and mixed-mode simulation/emulation

Contribute to projects requiring advanced verification tools such as Palladium Z1, HAPS, and Zebu platforms

Collaborate effectively within a team, ensuring high-quality deliverables

Job Requirements:

Possesses a Masters or Bachelors degree in Electrical Engineering or Computer Engineering

At least 3 years of relevant experience

Proficient in UVM, SystemVerilog, Verilog, Ethernet

Strong knowledge in protocols such as SPI, UART, and I2C

Excellent team player with strong communication skills.

#J-18808-Ljbffr

Apply Now

Similar Opportunities

View all jobs