Principal Systems Validation Engineer

Responsibilities

We are seeking a highly experienced PCI-Express (PCIe) Validation Expert to lead pre- and post-silicon validation efforts for high-speed storage accelerators. In this role, you will drive end-to-end PCIe validation, ensuring high-performance, standards compliance (PCIe Gen3/Gen4/Gen5 where applicable), and robust interoperability across a wide ecosystem. You will work cross-functionally with architecture, design, firmware, PHY, and system teams to define validation strategies, root-cause complex issues, and deliver high-quality silicon to production. You will focus on:

Own PCIe validation strategy and execution for the Storage Accelerator products across pre-silicon and post-silicon phases

Define coverage plans including protocol, link, PHY, power management, and compliance scenarios

Lead PCIe link bring-up, training, and tuning across multiple generations (Gen3/4/5/6)

Perform deep debug using protocol analyzers, oscilloscopes, and logic analyzers

Drive PCI-SIG compliance testing including electrical and protocol validation

Ensure interoperability with server CPUs from leading manufacturers

Develop and enhance automation frameworks (Python, C/C++) for validation scalability

Own and manage Functional Circuit Test (FCT) and In-Circuit Test (ICT) processes

Lead RMA analysis and work closely with customers and manufacturing teams to resolve board-level issues

Work closely with Architecture, Design, Software and Signal integrity teams

Coordinate Test program and test automation scripts development

Coaching Junior Engineering staff

Qualifications

Bachelor Degree or Master’s and above in Computer Engineering, Electrical/Electronics Engineering, or related field with at least 12 years or above of working experience in silicon validation or system validation with strong PCIe focus

Experienced with system validation in complex SoC (System on Chip) environment

Deep understanding of: PCIe protocol stack (Transaction, Data Link, Physical layers), PCIe power management, Link training and equalization

Hands-on experience with PCIe analysers. Scopes and signal integrity tools

Strong debugging skills in Hardware/Software co-debug

Experience with high speed Serdes tuning and validation methodologies

Familiar with system board design/debugging and usage of lab equipment like Oscilloscope and Logic analyzer

Good understanding in high-speed interface system/electrical verification & validation

Experience of C/C++ Programming and other test script development languages

In depth expertise of PCIe Gen3/Gen4/Gen5

Storage/Networking domain expertise is highly desirable

Knowledge of state-of-the-art data compression and cryptographic algorithms

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