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Uni Connect

Singapore / Global

Image Signal Processing (ISP) RTL Design Engineer

Job Description

Singapore, Singapore | Posted on 03/27/2025

Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)

Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation

Verify Logic at ISP level and Digital System level

Optimize Design for less gate count and low power consumption

Drive ISP Design activities in close collaboration with ISP Algorithm Team

Requirements

Minimum MSEE, or BSEE, or equivalent, plus 3+ years of Digital Design and verification related experience

Experience / knowledge in CMOS Image Sensor and image signal processing (ISP)

Experience / knowledge in System C/C++, System Verilog, and Catapult HLS tool.

Strong debugging and problem-solving skills

Good communication and interpersonal skills

Result oriented and embrace change behaviours

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Uni Connect

Image Signal Processing (ISP) RTL Design Engineer

Job Description

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